Field effect transistors normally operate as majority carrier devices, the on-resistance of which is established by channel geometry and resistivity. Examples of such devices are described in the U.S. patents to Tomisawa et al 4,187,514 and Terasawa et al 4,354,121.
In a conventional conductivity-modulated field effect transistor, one example of which is described in the above-referenced Terasawa et al patent, a gate region of a conductivity type opposite to that of the semiconductor material through which the channel is provided is formed in the upper surface of the device. (The device described in the Tomisawa et al patent is a junction field effect device, but it is not a conductivity-modulated JFET.)
A cross-sectional illustration of the configuration of a conventional conductivity-modulated hybrid gate (both junction and MOS gates) field effect transistor employed for high voltage applications (500-600 volts, with a breakdown voltage on the order of 700 volts) is shown in FIG. 1. For purposes of explanation, the device shown is an N channel device, comprising an N-type monocrystalline silicon region 15 formed in one surface 11 of a polysilicon substrate 10 and dielectrically isolated from the semiconductor material of the substrate 10 by a layer of dielectric isolation 12 (e.g. silicon dioxide) formed between the island region 15 and the substrate 10. Disposed in a first surface portion of the island region 15 is an N+ channel contact (cathode) region 13. Spaced apart from the channel contact region 13 is an opposite conductivity (P+) (anode) region 14 which forms a PN junction 17 with the semiconductor material of the island region 15. Minority carriers may be injected into the island region 15 by forward biasing the PN junction 17 formed between P+ region 14 and the N-type material of the island region 15.
For defining the effective operational geometry of the channel 16 of the FET, a junction gate region 18, having a conductivity (here P type) opposite to that (N) of the island region 15 is formed in a surface portion of the island region 15 between the channel contact (cathode) region 13 and the diode forming (anode) region 14. Gate region 18 defines a PN junction 19 with the semiconductor material of the island region 15 and extends to a depth D from the surface 11 of the island region 15, so as to define an effective thickness t of channel 16 formed between the bottom 20 of junction gate region 18 and the bottom 21 of the island region 15 therebeneath. In a channel conductivity-modulated FET, the resistance R.sub.c of the channel 16 can be reduced by conductivity modulating the channel 16 with minority carriers that are injected by forwarding biasing PN junction 17.
During a first mode of operation (on-state) of the device, in the absence of the application of a pinch-off voltage to the junction gate region 18, namely when the channel is conductive and the device is turned on, the on-resistance, Ron, of the channel 16 is defined as: EQU Ron=pL/tw (1)
where:
p=the resistivity of the conductivity-modulated channel 16, PA1 L=the length of the channel 16 PA1 t=the thickness of the channel 16, and PA1 w=the width of the channel 16 (the width being in a direction perpendicular to each of the length L and thickness t arrows shown in FIG. 1). PA1 q=electron charge, PA1 N=the coping concentration of the channel 16, and PA1 E=the dielectric constant of the channel 16.
For a second mode of operation (the off-state), the pinch off voltage for rendering the channel 16 effectively nonconductive is defined by: EQU V.sub.p =qNt.sup.2 /2E (2)
where:
From equations (1) and (2), it can be seen that the thickness t of the channel 16 must be kept small to hold the pinch off voltage V.sub.p at a low value, while the thickness t should be made large in order to reduce the on-resistance Ron.
In integrated circuit structures which require high voltage JFETs, the occupation area of the island region is typically quite large in order to provide the necessary channel thickness and depth of the island region to achieve the necessary high voltage characteristics. This large occupation area severely handicaps the integration density of the overall integrated circuit structure in which such a high voltage device is to be incorporated.
An additional limitation of a conventional conductivity-modulated field effect transistor structure is that it conducts and has modulated channel resistance only when the anode region 14 is at a higher voltage than the cathode region 13.
In a typical application of a conductivity-modulated field effect transistor to a switch incorporating a pair of devices for handling signals of both positive and negative voltage polarities, an anti-parallel connection as shown in FIG. 2 may be employed. As shown therein, a pair of conductivity-modulated field effect transistors Q1 and Q2 are connected in anti-parallel connection with the anode-cathode paths thereof intercoupled between terminals 1 and 2 and the gates thereof connected in common to a gate terminal 3. In this circuit configuration, transistor Q1 conducts when the voltage applied to terminal 1 is positive, while transistor Q2 conducts when the voltage applied to terminal 2 is positive. Obviously, the need to incorporate a pair of devices into a dual voltage polarity switch increases the required circuit occupation area and cost of manufacture of the switch device.
An additional shortcoming of a conventional conductivity-modulated field effect transistor is the fact that the device does not conduct until a diode forward voltage has been applied between the anode region and the cathode region. Since some circuit applications require that the switch employed conducted a lower voltage, the conventional conductivity-modulated field effect transistor cannot be utilized.